(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a contact hole whereby the size of the contact hole does not contract due to chemical processes subsequent to forming the contact hole.
(2) Description of the Prior Art
Semiconductor device manufacturing has been evolving ever since its inception whereby one of the driving forces behind this evolution has been to improve device performance while keeping device manufacturing costs under strict and competitive control. This evolution has over the years resulted in reducing device size down to where present day device dimensions are in the deep sub-micron range and are approaching 0.1 um. Device size reductions have resulted in significantly reducing such device performance detractors as parasitic capacitances and interconnect resistances, thereby significantly improving device operational speeds. The reduction in device size has not only resulted in improved device performance but has also allowed for increasing device densities so that the number of devices that can be fabricated using one wafer has increased considerably. Since the manufacturing of semiconductor devices requires the application of many diverse technical disciplines, the advances that have been made in device performance and in device density have been accomplished by numerous advances in these supporting technologies in addition to numerous advances in the design and functional characteristics of semiconductor devices. More particularly, advances in photolithography and the ways in which macro images are projected as micro images on target surfaces have greatly contributed to the progress that has been made. This coupled with advances in etching techniques, specifically Reactive Ion Etching (RIE), have been two of the major driving forces in advancing the semiconductor technology.
The advances that have been made over the years in semiconductor technology have however in many cases been made in small, incremental steps and have frequently required trade-offs and compromises in the best manner in which to implement particular improvements. These compromises are at times required due to problems of device yield and device reliability that are introduced as a consequence of device miniaturization. The invention specifically addresses one of these aspects of device creation that relates to the creation of contact holes. Contact holes are typically used to connect an overlying layer of metal interconnect lines to an underlying device region and can be fabricated having a width or diameter that is smaller than 0.5 um. The metal that is used to fill a contact hole of very small diameter must meet certain requirements of adhesion to the sidewalls of the hole, even and uniform distribution of the metal into and throughout the hole without forming key holes, low electric resistance and low contact resistance, no effects of electromigration or the formation of surface irregularities during its formation or during subsequent processing steps, and the like. For the reasons cited, aluminum, which typically has been used to form interconnect metal lines, is difficult to use for the filling of a contact hole. Aluminum is difficult to deposit using vapor deposition techniques while sputtering aluminum does not provide the desired conformal distribution of the aluminum throughout the cross section of the hole. Aluminum is moreover prone to electromigration, a phenomenon that is more likely to occur in holes of very small diameter due to the high current densities that pass through the metal fill of the contact hole. For these reasons, aluminum as a fill for contact holes is mostly replaced by tungsten that can be deposited with satisfactory results using low pressure CVD (LPCVD) techniques. Tungsten, in addition, can withstand high current concentrations whereby the tungsten remains conformally distributed throughout the contact opening.
As the density of circuit components contained within a semiconductor die has increased and the circuit components have decreased in size and are spaced closer together, it has become increasingly difficult to access selectively a particular region of the silicon wafer through the various layers that are typically superimposed on the surface of the silicon wafer without undesired interference with other active regions. It is especially important to have a technology that can etch openings that have essentially vertical walls, most notably when the openings are to extend deeply into the surface layers. Additionally, to tolerate some misalignment in the masks that are used to define such openings, it is advantageous to provide protection to regions that need isolation but that inadvertently lie partially in the path of the projected opening. To this end it is sometimes the practice to surround such regions with a layer of material that resists etching by the process being used to form the openings.
Using the conventional methods of forming contact holes, it is frequently found that the diameter of the contact hole is enlarged as a result of and after processing steps of wet chemistry treatment. It is apparent that, with the continuing shrinkage of device dimensions and the continuing increase in device density, the critical diameter (CD) of the contact hole is of importance whereby variations in the CD of contact holes are unacceptable. After the contact hole has been formed, the contact hole and its surrounding regions are, during subsequent processing steps, exposed to wet chemistry processing, such as photoresist stripping, which causes the enlargement of the diameter of the contact hole. It is therefore important to provide a method and sequence that prevents this from happening, the method of the invention addresses this concern.
Contact holes form an integral part of the fabrication of DRAM devices. This is further illustrated with the cross section of a typical DRAM that is shown in FIG. 1. The elements that constitute the DRAM memory cell that is shown in FIG. 1 are as follows:
10 is a substrate on the surface of which the DRAM memory cell is created
12 is an impurity implant in the surface of substrate 10 that functions as the bit line of the DRAM cell
13 and 14 provide the memory nodes of the memory cell
15 and 20 are th e two stacked memory cells that form the DRAM cell
16 are two thin layers of gate oxide that serve as stress relieve between the underlying substrate and the overlying gate electrodes
17 and 18 are the gate electrodes of the stacked memory cells whereby memory node 14, thin layer 16 (of gate oxide) and gate electrode 18 collectively form one of the two switching transistors of the stacked memory cell while memory node 13, thin layer 16 of gate oxide and gate electrode 17 collectively form the other of the two switching transistors of the stacked memory cell
22 is a thick layer of insulation that covers gate electrodes 17 and 18
23 and 24 are openings that have been created in layer 22 through which the memory nodes 13 and 14 are contacted
25 and 26 form the lower electrodes of the DRAM memory cell
28 is a thin layer of dielectric that serves as insulation layer of the two lower electrodes 25 and 26
30 is the upper electrode of the DRAM structure whereby lower electrode 26 with the thin dielectric layer 28 and the upper electrode 30 form a storage capacitor of the stacked memory cell 20 while lower electrode 25 with the thin dielectric layer 28 and the upper electrode 30 form a storage capacitor of the stacked memory cell 15, and
32 is a layer of insulation that isolates the DRAM memory structure.
The DRAM memory structure is further connected to the surrounding circuitry by depositing a layer of metal (not shown in FIG. 1) over the surface of layer 32 of insulation, typically aluminum, and patterning this layer to make contact with the bit line and capacitor regions of the DRAM structure.
The various openings that have been created in the DRAM structure and that are of interest to the process of the invention and that can serve as examples of the application of the invention are openings 23, 24 and 34, FIG. 1. It is clear from the cross section that is shown in FIG. 1 that in regions 36, 37 and 38 the critical dimensions of openings 23, 24 and 34 are of concern. If the diameter of these openings increases after the openings have been created, it is clear that a short can readily occur between for instance the gate electrode 16 and the lower electrode 25, the same applies to region 37 with the potential for a short developing between the gate electrode 18 and the lower electrode 26. Regions 38 have the same exposure with potentially electrical shorts developing between lower electrodes 25/26 and the upper electrode 30.
This is further and more generically highlighted in FIGS. 2a and 2b. FIG. 2a shows a cross section of a layer 40 wherein a conductor 42 is embedded, an opening 44 has been created in layer 40. FIG. 2b shows a cross section of the opening 44 of FIG. 2a after this openings has (inadvertently) been enlarged resulting in an opening 46 whereby conductor 42 now penetrates the sidewall of opening 46 and will therefore make electrical contact with the conductive fill that is used to fill opening 46. The process of the invention prevents the occurrence of the enlargement of the diameter of opening 44 (FIG. 2a ) and, with that, prevents the occurrence of electrical shorts.
A principle objective of the invention is to avoid contact hole shrinkage during processing steps of wet chemistry.
In accordance with the objectives of the invention a new method is provided to treat contact holes after hole formation has been completed. A layer of non-conformal dielectric is deposited over the surface in which the contact hole has been formed thereby including the sidewalls and bottom of the contact hole. The non-conformal dielectric will be unevenly deposited on the sidewalls and bottom of the contact hole with less non-conformal dielectric being deposited where the non-conformal dielectric has to penetrate deeper into the hole. This results in a relatively light deposition of non-conformal dielectric along the lower portions of the sidewalls and on the bottom of the contact hole with a heavier coating of non-conformal dielectric being deposited along the upper reaches of the contact hole. The objective of the invention is to prevent the enlargement of the hole diameter during subsequent processing steps, the relatively thick layer of non-conformal dielectric that is deposited along the upper reaches of the contact hole provides this prevention. The non-conformal dielectric can be removed from the bottom of the hole using a wet etch that further leaves the non-conformal dielectric in place along the sidewalls of the upper reaches of the contact hole.